sim_cfgbus.h

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// Copyright 2021-2025 The Aerospace Corporation.
// This file is a part of SatCat5, licensed under CERN-OHL-W v2 or later.
 
#pragma once
 
#include <deque>
#include <map>
#include <satcat5/cfgbus_core.h>
 
namespace satcat5 {
    namespace test {
        class CfgRegister : public satcat5::cfg::ConfigBus {
        public:
            CfgRegister();
 
            void read_default_none();
            void read_default_echo();
            void read_default(u32 val);
 
            // Cumulative read/write statistics.
            unsigned read_count() const;    
            unsigned write_count() const;   
 
            void read_push(u32 val);
            unsigned read_queue() const;
 
            u32 write_pop();
            unsigned write_queue() const;
 
            // Basic read and write operations for ConfigBus API.
            satcat5::cfg::IoStatus read(unsigned regaddr, u32& rdval) override;
            satcat5::cfg::IoStatus write(unsigned regaddr, u32 wrval) override;
 
        protected:
            // Queue of past write values and future read values.
            std::deque<u32> m_queue_rd;
            std::deque<u32> m_queue_wr;
 
            // Configure this register's read-response mode.
            enum class ReadMode {UNSAFE, STRICT, ECHO, CONSTANT};
            ReadMode m_rd_mode;
            u32 m_rd_dval;
 
            // Count total reads and writes.
            unsigned m_rd_count;
            unsigned m_wr_count;
        };
 
        class CfgDevice : public satcat5::cfg::ConfigBus {
        public:
            // Basic read and write operations for ConfigBus API.
            satcat5::cfg::IoStatus read(unsigned regaddr, u32& val) override;
            satcat5::cfg::IoStatus write(unsigned regaddr, u32 wrval) override;
 
            satcat5::test::CfgRegister& operator[](unsigned idx) {return reg[idx];}
 
            void irq_poll() {satcat5::cfg::ConfigBus::irq_poll();}
 
            void read_default_none();   // Read when empty = error
            void read_default_echo();   // Read when empty = last written
            void read_default(u32 val); // Read when empty = value
 
        protected:
            // Bank of underlying registers.
            satcat5::test::CfgRegister reg[satcat5::cfg::REGS_PER_DEVICE];
        };
 
        class CfgSpace : public satcat5::cfg::ConfigBus {
        public:
            // Basic read and write operations for ConfigBus API.
            satcat5::cfg::IoStatus read(unsigned regaddr, u32& val) override;
            satcat5::cfg::IoStatus write(unsigned regaddr, u32 wrval) override;
 
            void irq_poll() {satcat5::cfg::ConfigBus::irq_poll();}
 
            void add_device(unsigned devaddr, satcat5::cfg::ConfigBus& cfg);
 
            satcat5::cfg::ConfigBus& get_device(unsigned devaddr);
 
        protected:
            // Handler for undefined registers.
            satcat5::test::CfgRegister m_undef;
            // Bank of underlying registers.
            std::map<unsigned, satcat5::cfg::ConfigBus&> m_devs;
        };
    }
}