cfgbus_core.h

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// Copyright 2021-2025 The Aerospace Corporation.
// This file is a part of SatCat5, licensed under CERN-OHL-W v2 or later.
 
#pragma once
 
#include <satcat5/interrupts.h>
#include <satcat5/list.h>
 
#ifndef SATCAT5_CFGBUS_DIRECT
#define SATCAT5_CFGBUS_DIRECT   0
#endif
 
namespace satcat5 {
    namespace cfg {
        const unsigned DEVS_PER_CFGBUS  = 256;
        const unsigned REGS_PER_DEVICE  = 1024;
        const unsigned MAX_DEVICES      = 256;
        const unsigned MAX_TOTAL_REGS   = REGS_PER_DEVICE * MAX_DEVICES;
 
        const unsigned REGADDR_ANY      = 0;
 
        class WrappedRegister {
        public:
            WrappedRegister(ConfigBus* cfg, unsigned reg);
            operator u32();                             // Read from register
            void operator=(u32 wrval);                  // Write to register
            void write_repeat(unsigned count, const u32* data);
        protected:
            satcat5::cfg::ConfigBus* const m_cfg;       // Parent interface
            const unsigned m_reg;                       // Device + register index
        };
 
        class WrappedRegisterPtr {
        public:
            WrappedRegisterPtr(ConfigBus* cfg, unsigned reg);
            bool operator!() const;                     // Valid register?
            satcat5::cfg::WrappedRegister operator*();  // Pointer dereference
            satcat5::cfg::WrappedRegister operator[](unsigned idx);
            satcat5::cfg::WrappedRegisterPtr operator+(unsigned idx);
        protected:
            satcat5::cfg::ConfigBus* const m_cfg;       // Parent interface
            const unsigned m_reg;                       // Device + register index
        };
 
        // Prefer the direct or indirect interface?
        #if SATCAT5_CFGBUS_DIRECT
            typedef volatile u32* Register;
            #define SATCAT5_NULL_REGISTER 0
        #else
            typedef satcat5::cfg::WrappedRegisterPtr Register;
            #define SATCAT5_NULL_REGISTER satcat5::cfg::WrappedRegisterPtr(0,0)
        #endif
 
        enum class IoStatus {
            OK = 0,         // Operation successful
            BUSERROR,       // ConfigBus error
            CMDERROR,       // Invalid command
            TIMEOUT,        // Network timeout
        };
 
        // Constants for legacy compatibility (deprecated).
        constexpr auto IOSTATUS_OK =
            satcat5::cfg::IoStatus::OK;
        constexpr auto IOSTATUS_BUSERROR =
            satcat5::cfg::IoStatus::BUSERROR;
        constexpr auto IOSTATUS_CMDERROR =
            satcat5::cfg::IoStatus::CMDERROR;
        constexpr auto IOSTATUS_TIMEOUT =
            satcat5::cfg::IoStatus::TIMEOUT;
 
        class ConfigBus {
        public:
            virtual satcat5::cfg::IoStatus read(unsigned regaddr, u32& rdval) = 0;
            virtual satcat5::cfg::IoStatus write(unsigned regaddr, u32 wrval) = 0;
 
            virtual satcat5::cfg::IoStatus read_array(
                unsigned regaddr, unsigned count, u32* result);
            virtual satcat5::cfg::IoStatus read_repeat(
                unsigned regaddr, unsigned count, u32* result);
            virtual satcat5::cfg::IoStatus write_array(
                unsigned regaddr, unsigned count, const u32* data);
            virtual satcat5::cfg::IoStatus write_repeat(
                unsigned regaddr, unsigned count, const u32* data);
 
            inline unsigned get_regaddr(unsigned dev, unsigned reg) const
                {return satcat5::cfg::REGS_PER_DEVICE * dev + reg;}
 
            void register_irq(satcat5::cfg::Interrupt* obj);
            void unregister_irq(satcat5::cfg::Interrupt* obj);
 
            unsigned count_irq() const;
 
            satcat5::cfg::Register get_register(unsigned dev, unsigned reg = 0);
 
            void irq_poll();
 
        protected:
            // Constructor should only be called by children.
            // (Only children should create or destroy base class.)
            explicit ConfigBus(void* base_ptr = 0);
            ~ConfigBus() {}
 
            // Direct-access pointer, if applicable.
            volatile u32* m_base_ptr;
 
            // Linked-list of interrupt handlers.
            satcat5::util::List<satcat5::cfg::Interrupt> m_irq_list;
        };
 
        class ConfigBusMmap
            : public satcat5::cfg::ConfigBus
            , public satcat5::irq::Handler
        {
        public:
            ConfigBusMmap(void* base_ptr, int irq);
            ~ConfigBusMmap() {}
 
            // Basic read and write operations.
            satcat5::cfg::IoStatus read(unsigned regaddr, u32& val) override;
            satcat5::cfg::IoStatus write(unsigned regaddr, u32 val) override;
 
            void* get_device_mmap(unsigned dev) const;
 
            inline volatile u32* get_register_mmap(unsigned addr) const
                {return m_base_ptr + addr;}
 
        protected:
            void irq_event() override;
        };
    }
}