router2_offload.h

// Copyright 2024-2025 The Aerospace Corporation.
// This file is a part of SatCat5, licensed under CERN-OHL-W v2 or later.
// Offload port for gateware-accelerated IPv4 routers
 
#pragma once
 
#include <satcat5/cfgbus_interrupt.h>
#include <satcat5/router2_dispatch.h>
 
namespace satcat5 {
    namespace router2 {
        // Define policy configuration flags matching "router2_gateway.vhd".
        // Setting a policy mask blocks packets of the specified type.
        constexpr u32
            RULE_ALL        = (0xFFFF0000u),    
            RULE_LCL_BCAST  = (1u << 21),       
            RULE_NOIP_ALL   = (1u << 20),       
            RULE_NOIP_BCAST = (1u << 19),       
            RULE_IPV4_MCAST = (1u << 18),       
            RULE_IPV4_BCAST = (1u << 17),       
            RULE_BAD_DMAC   = (1u << 16);       
 
        class Offload
            : protected satcat5::cfg::Interrupt
            , protected satcat5::io::MultiWriter
        {
        public:
            Offload(
                satcat5::cfg::ConfigBusMmap* cfg, unsigned devaddr,
                satcat5::router2::Dispatch* router, unsigned hw_ports);
            ~Offload() SATCAT5_OPTIONAL_DTOR;
 
            void rule_allow(u32 mask);
            void rule_block(u32 mask);
            inline void rule_zpad(bool enable)
                { m_zero_pad = enable; }
 
            void deliver(const satcat5::eth::PluginPacket& meta);
 
            inline satcat5::cfg::Register get_log_register() const
                { return m_pktlog; }
 
            u32 reconfigure();
 
            inline u32 link_shdn_hw()
                { return m_ctrl->port_shdn; }
            inline SATCAT5_PMASK_TYPE link_shdn_sw()
                { return SATCAT5_PMASK_TYPE(link_shdn_hw()) << m_port_index; }
 
            inline unsigned port_index(unsigned hw_idx) const
                { return m_port_index + hw_idx; }
            inline SATCAT5_PMASK_TYPE port_mask(unsigned hw_idx) const
                { return satcat5::eth::idx2mask(port_index(hw_idx)); }
            inline SATCAT5_PMASK_TYPE port_mask_all() const
                { return m_port_mask; }
 
        protected:
            // Internal event-handlers.
            void irq_event() override;
 
            // Hardware register map:
            // TODO: Provide accessors for some of these hardware registers?
            struct ctrl_reg {
                u8 txrx_buff[1600];                 // Reg 0-399
                u32 rx_rsvd[89];                    // Reg 400-488
                volatile u32 pkt_log;               // Reg 489
                volatile u32 vlan_vid;              // Reg 490
                volatile u32 vlan_mask;             // Reg 491
                volatile u32 vlan_rate;             // Reg 492
                volatile u32 pkt_count;             // Reg 493
                volatile u32 port_shdn;             // Reg 494
                volatile u32 info;                  // Reg 495
                volatile u32 ecn_red;               // Reg 496
                volatile u32 nat_ctrl;              // Reg 497
                volatile u32 gateway;               // Reg 498
                volatile u32 tx_mask;               // Reg 499
                volatile u32 tx_ctrl;               // Reg 500
                volatile u32 ptp_2step;             // Reg 501
                volatile u32 port_count;            // Reg 502
                volatile u32 data_width;            // Reg 503
                volatile u32 core_clock;            // Reg 504
                volatile u32 table_size;            // Reg 505
                volatile u32 noip_data;             // Reg 506
                volatile u32 noip_ctrl;             // Reg 507
                volatile u32 cidr_data;             // Reg 508
                volatile u32 cidr_ctrl;             // Reg 509
                volatile u32 rx_irq;                // Reg 510
                volatile u32 rx_ctrl;               // Reg 511
                u32 port_cfg[512];                  // Reg 512-1023
            };
            ctrl_reg* const m_ctrl;
 
            // Connection to the parent object.
            satcat5::router2::Dispatch* const m_router;
            satcat5::cfg::Register m_pktlog;        // Packet-logging register
            const unsigned m_port_index;            // Index of hardware port #0.
            bool m_zero_pad;                        // Enable zero-padding?
            SATCAT5_PMASK_TYPE m_port_mask;         // Mask of all associated ports.
            u32 m_policy;                           // Block specific packet types?
        };
    }
}