cfgbus_timer.h

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// Copyright 2021-2024 The Aerospace Corporation.
// This file is a part of SatCat5, licensed under CERN-OHL-W v2 or later.
 
#pragma once
 
#include <satcat5/cfgbus_interrupt.h>
#include <satcat5/timeref.h>
 
namespace satcat5 {
    namespace cfg {
        class Timer
            : public satcat5::util::TimeRef
            , protected satcat5::cfg::Interrupt
        {
        public:
            Timer(satcat5::cfg::ConfigBus* cfg, unsigned devaddr)
                : Timer(cfg, devaddr, hw_ticks_per_sec(cfg, devaddr)) {}
 
            inline Timer(satcat5::cfg::ConfigBus* cfg, unsigned devaddr, u32 refclk_hz)
                : TimeRef(refclk_hz)
                , Interrupt(cfg, devaddr, REGADDR_TIMER_IRQ)
                , m_ctrl(cfg->get_register(devaddr))
                , m_callback(0)
            {
                m_ctrl[REGADDR_WDOG] = WDOG_PAUSE;
            }
 
            u32 raw() override;
 
            satcat5::util::TimeVal last_event();
 
            void timer_interval(unsigned usec);
 
            void timer_callback(satcat5::poll::OnDemand* callback);
 
            void wdog_disable();
 
            void wdog_update(u32 usec);
 
        protected:
            // Writing the special PAUSE value stops the watchdog.
            static constexpr u32 WDOG_PAUSE = (u32)(-1);
 
            // Define the hardware register map:
            static constexpr unsigned REGADDR_WDOG       = 0;
            static constexpr unsigned REGADDR_CPU_HZ     = 1;
            static constexpr unsigned REGADDR_PERF_CTR   = 2;
            static constexpr unsigned REGADDR_LAST_EVT   = 3;
            static constexpr unsigned REGADDR_TIMER_LEN  = 4;
            static constexpr unsigned REGADDR_TIMER_IRQ  = 5;
 
            // Access REGADDR_CPU_HZ before m_ctrl is initialized.
            static inline u32 hw_ticks_per_sec(satcat5::cfg::ConfigBus* cfg, unsigned devaddr) {
                satcat5::cfg::Register reg = cfg->get_register(devaddr);
                return reg[REGADDR_CPU_HZ];
            }
 
            // Timer interrupt handler.
            void irq_event() override;
 
            // Link to the hardware register map.
            satcat5::cfg::Register m_ctrl;
 
            // Callback object is polled after each timer interrupt.
            satcat5::poll::OnDemand* m_callback;
        };
    }
}