eth_sw_cache.h

// Copyright 2024-2025 The Aerospace Corporation.
// This file is a part of SatCat5, licensed under CERN-OHL-W v2 or later.
// MAC-address cache plugin for the software-defined Ethernet switch
 
#pragma once
 
#include <satcat5/eth_plugin.h>
#include <satcat5/lru_cache.h>
 
namespace satcat5 {
    namespace eth {
        class SwitchCacheInner : satcat5::eth::PluginCore {
        public:
            void query(satcat5::eth::PluginPacket& pkt) override;
 
            void set_miss_bcast(unsigned port_idx, bool enable);
 
            inline void set_miss_mask(SATCAT5_PMASK_TYPE mask)
                { m_miss_mask = mask; }
 
            inline SATCAT5_PMASK_TYPE get_miss_mask() const
                { return m_miss_mask; }
 
            inline unsigned mactbl_size() const         // Read maximum table length
                { return m_size; }
            bool mactbl_read(                           // Read Nth entry from table
                unsigned tbl_idx,                       // Table index to be read
                unsigned& port_idx,                     // Resulting port index
                satcat5::eth::MacAddr& mac_addr);       // Resulting MAC address
            bool mactbl_write(                          // Write new entry to table
                unsigned port_idx,                      // New port index
                const satcat5::eth::MacAddr& mac_addr); // New MAC address
            inline bool mactbl_clear()                  // Clear table contents
                { m_cache.clear(); return true; }
            inline bool mactbl_learn(bool enable)       // Enable automatic learning?
                { m_learn = enable; return true; }
            inline bool mactbl_learn() const            // Learning enabled?
                { return m_learn; }
 
        protected:
            struct CacheEntry {
            public:
                CacheEntry() = default;
                CacheEntry(const CacheEntry& t) = delete;
                CacheEntry& operator=(const CacheEntry& t) = delete;
 
                u64 m_key;              
                unsigned m_port;        
            private:
                friend satcat5::util::LruCache<CacheEntry>;
                CacheEntry* m_next;     
            };
 
            SwitchCacheInner(
                satcat5::eth::SwitchCore* sw,
                CacheEntry* array, unsigned size);
 
            SATCAT5_PMASK_TYPE destination_mask(const PluginPacket& pkt);
 
            // Internal configuration?
            bool m_learn;                       // Enable learning?
            SATCAT5_PMASK_TYPE m_miss_mask;     // Cache miss policy
 
            // Backing array and LRU cache for MAC addresses.
            CacheEntry* const m_array;
            const unsigned m_size;
            satcat5::util::LruCache<CacheEntry> m_cache;
        };
 
        template <unsigned SIZE = 64>
        class SwitchCache : public satcat5::eth::SwitchCacheInner {
        public:
            explicit SwitchCache(satcat5::eth::SwitchCore* sw)
                : SwitchCacheInner(sw, m_table, SIZE) {}
        protected:
            satcat5::eth::SwitchCacheInner::CacheEntry m_table[SIZE];
        };
    }
}